Process monitor circuits are used in semiconductor manufacturing processes to monitor, at various points during production, whether the processes are producing semiconductor devices that perform according to specification. Monitoring is typically done by measuring the characteristics of the monitor circuit that are related to the process conditions used to fabricate the circuit. The process monitor circuits may be placed within every one of the production circuits, or dice, produced. In this manner, the process monitor circuit in each packaged device can be used as a data point to determine process characteristics.
This design goal has been more difficult to achieve as processing technology has advanced, and semiconductor devices operate at increasingly greater speeds. This is because the size of certain process monitor circuits has needed to increase as the speed of the semiconductor devices has increased. Increasing the size of the process monitor requires the production dice to be larger. Making the production dice larger is contrary to general design goals, as it results in a more expensive device.
For example, one important process monitor for CMOS circuitry is the speed at which the gate can switch. Thus, a typical process monitor circuit designed to measure gate speed might have two signal paths. One of the paths is designed to transmit a signal quickly, and the other is designed to transmit a signal with a delay that is proportional to the gate switching speed. Customarily, several transistors may be connected in series for the delayed signal path. The difference in the length of time required for the signal to traverse the quick path and the delayed path gives an indication of the speed of the transistor gates.
However, as gate switching speeds have increased, the difference between the times required for the signals to traverse the two paths has decreased to the point that automated test equipment cannot conveniently and accurately measure the difference. Thus, additional transistors are placed in series in the delayed signal path, increasing the amount of time required by the signal traversing the path. Therefore, as device speeds increase, more and more transistors are added to the circuit so that it can be accurately tested. The additional transistors require additional surface area in the production dice.
Adding to the problem is the desired capability to take multiple, independent measurements on process monitor circuits. For instance, it is beneficial to have independent measurements for both PMOS gates and NMOS gates in the example given above. Adding such capability, however, has typically compounded the problem of size limitations and resulted in excessively large process monitor circuits.
Yet another problem encountered is the number of input and output lines required. While as much information as possible is desired from such circuits, they compete with the production circuit for a limited number of pin-outs on the package.
What is needed, therefore, is a digital process monitor circuit that requires relatively fewer gates and less of an increase in surface area on the wafer in order to accurately measure gate speeds as semiconductor device speeds increase, allows for independent measurement of NMOS and PMOS gates, and requires few pin-outs.